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1 ? fn7456.3 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005, 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. isl59424, isl59445 1ghz triple multiplexing amplifiers the isl59424, isl59445 are 1ghz bandwidth multiplexing amplifiers designed primarily for video input switching. these mux-amps exhibit a fixed gain of 1 and also feature a high speed three-state to enable the output of multiple devices to be wired together. all logic inputs have pull-downs to ground and may be left floating. the en pin, when pulled high, sets the isl59424, isl59445 in to low current mode-consuming just 15mw. an added feature in the isl59424 is a latch enable function (le ) that allows independent logic control using a common logic bus. when le is high the last logic state is preserved . features ? triple 2:1 and 4:1 multiplexers for rgb ? internally set gain-of-1 ? high speed three-state outputs (hiz) ? power-down mode (en ) ? latch enable (isl59424) ? 5v operation ? 1200 v/sec slew rate ? 1ghz bandwidth ? latched select pin (isl59424) ? pb-free (rohs compliant) applications ? hdtv/dtv analog inputs ? video projectors ? computer monitors ? set-top boxes ? security video ? broadcast video equipment table 1. channel select logic table isl59424 s0 enable hiz le output 0 0 0 0 ino (a, b, c) 1 0 0 0 in1 (a, b, c) x 1 x x power down x 0 1 x high z x 0 0 1 last s0 state preserved table 2. channel select logic table isl59445 s1 s0 enable hiz output 0 0 0 0 in0 (a, b, c) 0 1 0 0 in1 (a, b, c) 1 0 0 0 in2 (a, b, c) 1 1 0 0 in3 (a, b, c) x x 1 x power down xx 0 1 high z ordering information part number (notes 1, 2, 3) part marking package (pb-free) pkg. dwg. # isl59424irz 59424 irz 24 ld qfn mdp0046 isl59424irz-t13 59424 irz 24 ld qfn mdp0046 isl59424irz-t7 59424 irz 24 ld qfn mdp0046 isl59445irz 59445 irz 32 ld qfn l32.5x6a isl59445irz-t13 59445 irz 32 ld qfn l32.5x6a isl59445irz-t7 59445 irz 32 ld qfn l32.5x6a ISL59445IRZ-EVAL evaluation board notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic pa ckaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity lev el (msl), please see device information page for isl59424 and isl59445 . for more information on msl please see techbrief tb363 . 4. 32 ld qfn exposed pad size 2.48 x 3.40mm. data sheet september 30, 2011
2 fn7456.3 september 30, 2011 pinouts isl59424 (24-ld qfn) top view isl59445 (32-ld qfn) top view functional diagram isl59424 functional diagram isl59445 19 18 17 16 15 14 13 24 23 22 21 20 8 9 10 11 12 1 2 3 4 5 6 7 in0b nic in0c gndb in1a gndc in1b en able outa v+ outb v- outc s0 gnda in0a nic nic hiz nic in1c nic nic le thermal pad a = 1 a = 1 a = 1 latched on high le nic = no internal connection thermal pad internally connected to v-. pad must be tied to v- thermal pad 25 24 23 22 21 20 19 32 31 30 29 28 10 11 12 13 14 1 2 3 4 5 6 7 in1a nic in1b nic in1c gndb in2a en able nic v+ outa v- outb outc gnda in0a nic in0b nic in2c gndc in3a nic in3b 8 9 18 17 15 27 16 26 s0 s1 nic in3c nic in2b in0c hiz a = 1 a = 1 a = 1 thermal pad internally connected to v-. pad must be tied to v- nic = no internal connection out decode in0 (a, b, c) in1 (a, b, c) c c le s0 enable d l q d l q en0 en1 hiz a logic high on le will latch the last s0 state. this logic state is preserved when cycling hiz or enable functions. amplifier bias decode in0 (a, b, c) in1 (a, b, c) in2 (a, b, c) in3 (a, b, c) s0 s1 en0 en1 en3 en2 out hiz enable amplifier bias isl59424, isl59445
3 fn7456.3 september 30, 2011 absolute maxi mum ratings (t a = +25c) thermal information supply voltage (v+ to v-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . v- -0.5v, v+ +0.5v supply turn-on slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1v/s digital & analog input current (note 5) . . . . . . . . . . . . . . . . . . 50ma output current (continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50ma esd rating human body model (per mil-st d-883 method 3 015.7). . . .2500v machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300v thermal resistance (typical, notes 6, 7) ja (c/w) jc (c/w) 24 ld qfn . . . . . . . . . . . . . . . . . . . . . . 46 10 32 ld qfn . . . . . . . . . . . . . . . . . . . . . . 46 10 storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c operating junction temperature . . . . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. if an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values. 6. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 7. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v+ = +5v, v- = -5v, gnd = 0v, t a = +25c, v in = 1v p-p & r l = 500 to gnd unless otherwise specified. parameter description conditions min typ max unit general i s enabled enabled supply current (isl59424) no load, v in = 0v, enable low, i s + 353943ma no load, v in = 0v, enable low, i s - -40 -36 -32 ma enabled supply current (isl59445) no load, v in = 0v, enable low, i s + 475360ma no load, v in = 0v, enable low, i s - -57 -50 -44 ma +i s disabled disabled s upply current enable high, i s + 234ma enable high, i s --500-a i b input bias current v in = 0 -3.4 -2.2 -1.4 a i tri bias current into output, hiz mode isl59424 - v out = +5v 8 15 22 a isl59445 - v out = 0v -35 0 35 a v out positive and negative output swing v in = 3.5v 3.2 3.4 - v i out output current r l = 10 to gnd 80 130 - ma v os offset voltage -13 3 13 mv r out hiz output resistance hiz = logic high - 1.0 - m r out enabled output resistance hiz = logic low - 0.2 - r in input resistance v in = 3.5v - 10 - m a cl or a v voltage gain v in = 1.5v 0.98 0.99 1.0 v/v logic v ih input high voltage (logic inputs) 2 - - v v il input low voltage (logic inputs) - - 0.8 v i ih input high current (logic inputs) v h = 5v 235 270 320 a i il input low current (logic inputs) v l = 0v - 1 3 a ac general psrr power supply rejection ratio (isl59424) dc, psrr v+ and v- combined 60 73 - db power supply rejection ratio (isl59445) dc, psrr v+ and v- combined 50 57 - db isl59424, isl59445
4 fn7456.3 september 30, 2011 iso channel isolation (isl59424) f = 10mhz, c l = 0.5pf, v in = -6dbm - 80 - db channel isolation (isl59445) - 75 - db xtalk channel cross talk (isl59424) f = 10mhz, c l = 0.5pf, v in = -6dbm - 75 - db channel cross talk (isl59445) - 70 - - dg differential gain error ntc-7, r l = 150, c l = 0.5pf - 0.02 - % dp differential phase error ntc-7, r l = 150, c l = 0.5pf - 0.02 - bw -3db bandwidth c l = 0.5pf - 1000 - mhz fbw 0.1db bandwidth c l = 0.5pf - 130 - mhz 0.1db bandwidth cl = 1.5pf - 200 - mhz switching characteristics sr slew rate 25% to 75%, r l = 150 , input enabled, c l = 1.5pf, v in = 1v - 1200 - v/s v glitch isl58424 channel-to-channel switching glitch v in = 0v, c l = 0.5pf - 40 - mv p-p enable switching glitch v in = 0v, c l = 0.5pf - 300 - mv p-p hiz switching glitch v in = 0v, c l = 0.5pf - 200 - mv p-p v glitch isl59445 channel-to-channel switching glitch v in = 0v, c l = 0.5pf - 20 - mv p-p enable switching glitch v in = 0v, c l = 0.5pf - 200 - mv p-p hiz switching glitch v in = 0v, c l = 0.5pf - 200 - mv p-p t sw-l-h channel switching time low-to-high 1.2v logic threshold to 10% movement of analog output -15-ns t sw-h-l channel switching time high-to-low 1.2v logic threshold to 10% movement of analog output -15-ns tr rise time 10% to 90% - 600 - ps tf fall time 10% to 10% - 800 - ps tpd propagation delay 10% to 10% - 600 - ps t s 0.1% settling time step = 1v - 6 - ns t lh latch enable holdtime le = 0v - 10 - ns electrical specifications v+ = +5v, v- = -5v, gnd = 0v, t a = +25c, v in = 1v p-p & r l = 500 to gnd unless otherwise specified. parameter description conditions min typ max unit typical performance curves v s = 5v, r l = 500 to gnd, t a = +25c, unless otherwise specified. figure 1. gain vs frequency vs c l figure 2. gain vs frequency vs r l -10 -8 -6 -4 -2 0 2 4 6 8 10 1 10 100 1k frequency (mhz) normalized gain (db) source power = -12dbm c l includes 0.5pf board capacitance 1.2k c l = 2.7pf c l = 5.2pf c l = 3.8pf c l = 1.5pf c l = 0.5pf c l = 8.7pf -5 -4 -3 -2 -1 0 1 2 3 4 5 1 10 100 1.2k frequency (mhz) normalized gain (db) r l = 1k source power = -12dbm 1k r l = 100 r l = 500 r l = 150 isl59424, isl59445
5 fn7456.3 september 30, 2011 figure 3. 0.1db gain vs frequency figure 4. r out vs frequency figure 5. isl59424 transient response figure 6. isl59445 transient response figure 7. isl59424 crosstalk and off-isolation figure 8. isl59445 crosstalk and off-isolation typical performance curves v s = 5v, r l = 500 to gnd, t a = +25c, unless otherwise specified. (continued) 10 100 1.2k normalized gain (db) source power = -12dbm -0.7 -0.6 -0.4 -0.3 -0.1 0 0.1 -0.2 -0.5 1 c l = 2.0pf c l = 0.5pf 0.2 -0.8 1k c l = 1.5pf frequency (mhz) 100 10 1 0.1 0.1 1 10 100 1k frequency (mhz) output resistance ( ) source power = -12dbm isl59424 isl59445 output voltage (v) time (5ns/div) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 c l = 1.5pf r l = 500 0.8 -0.8 output voltage (v) time (5ns/div) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 c l = 1.5pf r l = 500 -0.8 0.8 frequency (mhz) -10 -30 -50 (db) 0.1 1 10 100 1k -70 -90 input x to output y crosstalk off-isolation input x to output x 0 -20 -40 -60 -80 -100 frequency (mhz) -10 -30 -50 (db) 0.1 1 10 100 -70 -90 input x to output y crosstalk 0 -20 -40 -60 -80 -100 1k off-isolation input x to output x isl59424, isl59445
6 fn7456.3 september 30, 2011 figure 9. isl59424 psrr channels a, b, c figure 10. isl59445 psrr channels a, b, c figure 11. channel-to-channel switching glitch v in = 0v figure 12. channel-to-channel transient response v in = 1v figure 13. enable switching glitch v in = 0v figure 14. enable transient response v in = 1v typical performance curves v s = 5v, r l = 500 to gnd, t a = +25c, unless otherwise specified. (continued) frequency (mhz) 0 -10 -30 psrr (db) 0.3 1 10 100 1k -50 -70 psrr (v-) 10 -20 -40 -60 -80 20 psrr (v+) frequency (mhz) 0 -10 -30 psrr (db) 0.3 1 10 100 1k -50 -70 10 -20 -40 -60 20 -80 psrr (v+) psrr (v-) 1v/div 20mv/div v out a, b, c 10ns/div 0 0 v in = 0v s0, s1 50 term. 1v/div 0.5v/div 10ns/div 0 0 v in = 1v v out a, b, c s0, s1 50 term. 1v/div 100mv/div 20ns/div 0 0 v in = 0v v out a, b, c enable 50 term. v in = 1v 1v/div 1v/div 0 0 v out a, b, c enable 50 term. 20ns/div isl59424, isl59445
7 fn7456.3 september 30, 2011 figure 15. hiz switching glitch v in = 0v figure 16. hiz transient response v in = 1v figure 17. input noise vs frequency (output a, b, c) typical performance curves v s = 5v, r l = 500 to gnd, t a = +25c, unless otherwise specified. (continued) 1v/div 200mv/div 10ns/div 0 0 v in = 0v v out a, b, c hiz 50 term. v in = 1v 1v/div 1v/div 10ns/div 0 0 v out a, b, c 50 term. hiz 60 50 40 30 20 10 0 100 1k 10k 100k frequency (hz) voltage noise (nv hz) isl59424, isl59445
8 fn7456.3 september 30, 2011 pin descriptions isl59445 (32-ld qfn) isl59424 (24-ld qfn) pin name equivalent circuit description 1 5 in1a circuit 1 channel 1 input for output amplifier "a" 2, 4, 8, 13, 15, 24, 28, 30 2, 8, 10, 11, 21, 22 nic - n ot i nternally c onnected; it is recommended these pins be tied to ground to minimize crosstalk. 3 7 in1b circuit 1 channel 1 input for output amplifier "b" 5 9 in1c circuit 1 channel 1 input for output amplifier "c" 6 4 gndb circuit 4 ground pin for output amplifier ?b? 7 in2a circuit 1 channel 2 input for output amplifier "a" 9 in2b circuit 1 channel 2 input for output amplifier "b" 10 in2c circuit 1 channel 2 input for output amplifier "c" 11 6 gndc circuit 4 ground pin for output amplifier ?c? 12 in3a circuit 1 channel 3 input for output amplifier "a" 14 in3b circuit 1 channel 3 input for output amplifier "b" 16 in3c circuit 1 channel 3 input for output amplifier "c" 17 s1 circuit 2 channel selection pin msb (binary logic code) 18 13 s0 circuit 2 channel selection pin. lsb (binary logic code) 19 14 outc circuit 3 output of amplifier ?c? 20 16 outb circuit 3 output of amplifier ?b? 21 15 v- circuit 4 negative power supply 22 18 outa circuit 3 output of amplifier ?a? 23 17 v+ circuit 4 positive power supply 25 19 enable circuit 2 device enable (a ctive low). internal pull-down resi stor ensures the device will be active with no connection to this pin. a logic high on this pin puts device into power-down mode. in power-down mode only logic circuitry is active. all logic states are preserved post power-down. this state is not recommended for logic control where more than one mux-amp share the same video output line. 12 le circuit 2 device latch enable on the isl59424. a logic high on le will latch the last (s0, s1) logic state. hiz and enable functions are not latched with the le pin. 26 20 hiz circuit 2 output disable (active high). inter nal pull-down resistor ens ures the device will be active with no connection to this pin. a logic high, puts the outputs in a high impedance state. use this state to c ontrol logic when more than one mux-amp share the same video output line. 27 3 in0c circuit 1 channel 0 for output amplifier "c" 29 1 in0b circuit 1 channel 0 for output amplifier "b" 31 23 in0a circuit 1 channel 0 for output amplifier "a" 32 24 gnda circuit 4 ground pin for output amplifier ?a? in v+ v- logic pin v+ v- gnd 33k 21k + - 1.2v v+ v- out circuit 3 circuit 1 circuit 2 v- v+ gnd capacitively coupled esd clamp gndc gnda circuit 4 v- thermal heat sink pad ~1m substrate isl59424, isl59445 .
9 fn7456.3 september 30, 2011 figure 18a illustrates the optimum output load for testing ac performance. figure 18b illustra tes the optimum output load when connecting to 50 input terminated equipment. application information general the isl59424, isl59445 are triple 2:1 and 4:1 muxes that are ideal for the matrix element of high performance switchers and routers. the isl59424, isl59445 are optimized to drive a 1.5pf in parallel with a 500 load. the capacitance can be split between the pcb capacitance an and external load capacitance. their low input capacitance and high input resistance provide excellent 50 or 75 terminations. ground connections for the best isolation and cro sstalk rejection, all gnd pins and nic pins must connect to the gnd plane. control signals s0, s1, enable , le , hiz - these pins are binary coded, ttl/cmos compatible control inputs. the s0, s1 pins select which one of the inputs connect to the output. all three amplifiers are switched simultan eously from their respective inputs. the enable , le , hiz pins are used to disable the part to save power, latch in the last logic state and three-state the output amplifiers, respectively. for control signal rise and fall times less than 10ns the use of termination resistors close to the part should be considered to minimize transients coupled to the output. power-up considerations the esd protection circuits use internal diodes from all pins the v+ and v- supplies. in addition, a dv/dt- triggered clamp is connected between the v+ and v- pins, as shown in the equivalent circuits 1 through 4 section of the ?pin descriptions? on page 8. the dv/dt triggered clamp imposes a maximum supply turn-on slew rate of 1v/s. damaging currents can flow for power supply rates-of-rise in excess of 1v/s, such as during hot plugging. under these conditions, additional methods should be employed to ensure the rate of rise is not exceeded. consideration must be given to the order in which power is applied to the v+ and v- pins, as well as analog and logic input pins. schottky diodes (motorola mbr0550t or equivalent) connected from v+ to ground and v- to ground (figure 19) will shunt damaging currents away from the internal v+ and v- esd diodes in the event that the v+ supply is applied to the device before the v- supply. if positive voltages are applied to the logic or analog video input pins before v+ is applied, current will flow through the internal esd diodes to the v+ pin. the presence of large decoupling capacitors and the loading effect of other circuits connected to v+, can result in damaging currents through the esd diodes and other active circuits within the device. therefore, adequate current lim iting on the digital and analog inputs is needed to prevent damage during the time the voltages on these inputs are more positive than v+. ac test circuits figure 18a. test circuit with optimal output load figure 18b. test circuit for measuring with 50 or 75 input terminated equipment figure 18c. backloaded test circuit for video cable application. bandwidth and linearity for r l less than 500 will be degraded. figure 18. test circuits isl59424, isl59445 c l 50 v in 500 r l 1.5pf or 75 isl59424, isl59445 r s c l v in 475 test 1.5pf 50 or 75 50 or 75 50 or 75 equipment or 462.5 isl59424, isl59445 r s c l v in 50 or 75 test 1.5pf 50 or 75 50 or 75 equipment isl59424, isl59445
10 fn7456.3 september 30, 2011 hiz state an internal pull-down resistor connected to the hiz pin ensures the device will be active with no connection to the hiz pin. the hiz state is es tablished within approximately 15ns (figure 16) by placing a logic high (>2v) on the hiz pin. if the hiz state is selected, the output is a high impedance 1.4m with approximately 1.5pf in parallel with a 10 a bias current from the output. use this state to control the logic when more than one mux shares a common output. in the hiz state the output is three-stated, and maintains its high z even in the presence of high slew rates. the supply current during this state is basically the same as the active state. enable and power down states the enable pin is active low. an internal pull-down resistor ensures the device will be active with no connection to the enable pin. the power down state is established within approximately 100ns (figure 14), if a logic high (>2v) is placed on the enable pin. in the power down state, the output has no leakage but has a large variable capacitance (on the order of 15pf), and is capable of being back-driven. under this condition, large in coming slew rates can cause fault currents of tens of ma. do not use this state as a logic control for applications driving more than one mux on a common output. le state the isl59424 is equipped with a latch enable pin. a logic high (>2v) on the le pin latches the last logic state. this logic state is preserved when cycling hiz or enable functions. limiting the output current no output short circuit current li mit exists on these parts. all applications need to limit the output current to less than 50ma. adequate thermal heat si nking of the parts is also required. application example figure 19 illustrates the use of the isl59445, two isl84517 spst switches and one nc7st00p5x nand gate to mux 3 different component video signals and one rgb video signal. the spdt switches provide the sync signal for the rgb video and disconnects the sync signal for the component signal. pc board layout the frequency response of this circuit depends greatly on the care taken in designing the pc board. the following are recommendations to achieve optimum high frequency performance from your pc board. ? the use of low inductance components such as chip resistors and chip capacitors is strongly recommended. ? minimize signal trace lengths. trace inductance and capacitance can easily limit circuit performance. avoid sharp corners, use rounded corners when possible. vias in the signal lines add inductance at high frequency and should be avoided. pcb traces greater than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. high frequency performance may be degraded for traces greater than one inch, unless strip line are used. ? match channel-to-channel analog i/o trace lengths and layout symmetry. this will minimize propagation delay mismatches. ? maximize use of ac de-coupled pcb layers. all signal i/o lines should be routed over continuous ground planes (i.e. no split planes or pcb gaps under these lines). avoid vias in the signal i/o lines. ? use proper value and location of termination resistors. termination resistors should be as close to the device as possible. ? when testing use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. ? minimum of 2 power supply de-coupling capacitors are recommended (1000pf, 0.01f) as close to the devices as possible - avoid vias between the capacitor and the device because vias add unwanted inductance. larger caps can be farther away. when vias are required in a layout, they should be routed as far away from the device as possible. v+ v+ v- v- v+ v- v+ v- logic control gnd in0 in1 s0 out external circuits schottky protection v+ v- power gnd signal logic v+ supply v- supply de-coupling caps figure 19. schottky protection circuit isl59424, isl59445
11 fn7456.3 september 30, 2011 ? the nic pins are placed on both sides of the input pins. these pins are not internally connected to the die. it is recommended these pins be tied to ground to minimize crosstalk. the qfn package requires additional pcb layout rules for the thermal pad the thermal pad is electrically connected to v- supply through the high resistance ic substrate. its primary function is to provide heat sinking for the ic. however, because of the connection to the v- supply through the substrate, the thermal pad must be tied to the v- supply to prevent unwanted current flow to the thermal pad. do not tie this pin to gnd. connecting this pin to gnd could result in large back biased currents flowing between gnd and v-. the isl59445 uses the package with pad dimensions of d2 = 2.48mm and e2 = 3.4mm. maximum ac performance is achieved if the thermal pad is attached to a dedicated de-couple d layer in a multi-layered pc board. in cases where a dedicated layer is not possible, ac performance may be reduc ed at upper frequencies. the thermal pad requirements are proportional to power dissipation and ambient temperature. a dedicated layer eliminates the need for individual thermal pad area. when a dedicated layer is not possible a 1? x 1? pad area is sufficient for the isl59445 that is dissipa ting 0.5w in +50c ambient. pad area requirements should be evaluated on a case by case basis. isl59424, isl59445
12 fn7456.3 september 30, 2011 figure 20. application showing three ypbpr channels and one rgb+hv channel pb1 pb2 pb3 g pr1 pr2 pr3 b inoa in1a in2a in3a inob in1b in2b in3b inoc in1c in2c in3c 31 1 7 12 29 3 9 14 27 5 10 16 isl59445il s0 s1 h sync v sync 18 17 outc 19 20 outb outa 22 v- v+ 5v -5v 0.1f 0.1f 1nf 1nf y1 y2 y3 r r1 75 r2 75 r3 75 r5 75 r7 75 r9 75 r4 75 r6 75 r8 75 r11 75 r10 75 r12 75 gnda gndb gndc nic nic nic nic nic nic nic nic 32 6 11 2 4 8 13 15 24 28 30 isl84517ih-t com 1 nc 2 v- v+ 5v -5v 0.1f 0.1f 1nf 1nf in 4 nc7st00p5x out 4 input 1 input 2 5v 0.1f 1nf 5v gnd 23 21 enable logic inputs 25 hiz 26 r16 500 r17 500 r18 500 3 5 3 5 isl84517ih-t com 1 nc 2 v- v+ 5v -5v 0.1f 0.1f 1nf 1nf in 4 3 5 sc70 sot-23 sot-23 qfn optional schottky protection isl59424, isl59445
13 fn7456.3 september 30, 2011 isl59424, isl59445 qfn (quad flat no-lead) package family pin #1 i.d. mark 2 1 3 (n-2) (n-1) n (n/2) 2x 0.075 top view (n/2) ne 2 3 1 pin #1 i.d. (n-2) (n-1) n b l n leads bottom view detail x plane seating n leads c see detail "x" a1 (l) n leads & exposed pad 0.10 side view 0.10 b a m c c b a e 2x 0.075 c d 3 5 7 (e2) (d2) e 0.08 c c (c) a 2 c mdp0046 qfn (quad flat no-lead) package family (compliant to jedec mo-220) symbol millimeters tolerance notes qfn44 qfn38 qfn32 a 0.90 0.90 0.90 0.90 0.10 - a1 0.02 0.02 0.02 0.02 +0.03/-0.02 - b 0.25 0.25 0.23 0.22 0.02 - c 0.20 0.20 0.20 0.20 reference - d 7.00 5.00 8.00 5.00 basic - d2 5.10 3.80 5.80 3.60/2.48 reference 8 e 7.00 7.00 8.00 6.00 basic - e2 5.10 5.80 5.80 4.60/3.40 reference 8 e 0.50 0.50 0.80 0.50 basic - l 0.55 0.40 0.53 0.50 0.05 - n 44 38 32 32 reference 4 nd 11 7 8 7 reference 6 ne 11 12 8 9 reference 5 symbol millimeters toler- ance notes qfn28 qfn24 qfn20 qfn16 a 0.90 0.90 0.90 0.90 0.90 0.10 - a1 0.02 0.02 0.02 0.02 0.02 +0.03/ -0.02 - b 0.25 0.25 0.30 0.25 0.33 0.02 - c 0.20 0.20 0.20 0.20 0.20 reference - d 4.00 4.00 5.00 4.00 4.00 basic - d2 2.65 2.80 3.70 2.70 2.40 reference - e 5.00 5.00 5.00 4.00 4.00 basic - e2 3.65 3.80 3.70 2.70 2.40 reference - e 0.50 0.50 0.65 0.50 0.65 basic - l 0.40 0.40 0.40 0.40 0.60 0.05 - n 28 24 20 20 16 reference 4 nd 6 5 5 5 4 reference 6 ne 8 7 5 5 4 reference 5 rev 11 2/07 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. tiebar view shown is a non-functional feature. 3. bottom-side pin #1 i.d. is a diepad chamfer as shown. 4. n is the total number of terminals on the device. 5. ne is the number of terminal s on the ?e? side of the package (or y-direction). 6. nd is the number of terminals on the ?d? side of the package (or x-direction). nd = (n/2)-ne. 7. inward end of terminal may be squar e or circular in shape with radius (b/2) as shown. 8. if two values are listed, multiple exposed pad options are available. refer to device-specific datasheet.
14 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7456.3 september 30, 2011 isl59424, isl59445 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) pin #1 i.d. mark 2 1 3 (n-2) (n-1) n (n/2) 2x 0.075 top view (n/2) ne 2 3 1 pin #1 i.d. (n-2) (n-1) n b l n leads bottom view detail x plane seating n leads c see detail "x" a1 (l) n leads & exposed pad 0.10 side view 0.10 b a m c c b a e 2x 0.075 c d 3 5 7 (e2) (d2) e 0.08 c c (c) a 2 c l32.5x6a (one of 10 packages in mdp0046) 32 lead quad flat no-lead plastic package (compliant to jedec mo-220) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 0.00 0.02 0.05 - d 5.00 bsc - d2 2.48 ref - e 6.00 bsc - e2 3.40 ref - l 0.45 0.50 0.55 - b 0.17 0.22 0.27 - c 0.20 ref - e 0.50 bsc - n 32 ref 4 nd 7 ref 6 ne 9 ref 5 rev 1 2/09 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. tiebar view shown is a non-functional feature. 3. bottom-side pin #1 i.d. is a diepad chamfer as shown. 4. n is the total number of terminals on the device. 5. ne is the number of terminals on the ?e? side of the package (or y-direction). 6. nd is the number of terminals on the ?d? side of the package (or x-direction). nd = (n/2)-ne. 7. inward end of terminal may be s quare or circular in shape with radius (b/2) as shown.

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